A flash memory is one of the popular non-volatile memories. Generally, flash memories can be classified into two types, that is, NOR flash memories and NAND flash memories. Since the erase speed of the NAND flash memory is faster and the area of each storage unit is smaller, the applications of the NAND flash memory are more extensive.
A NAND flash memory chip usually consists of plural blocks. Each block includes plural transistors (or cells) that are connected with each other in series. While a read operation, a write operation or an erase operation is performed, a memory controller provides corresponding voltages to the gate terminals, source terminals and drain terminals of the cells through a row decoder.
As known, the flash memory can only be erased in blocks units. Moreover, the NAND flash memory usually has global common source line (hereinafter, GCSL) architecture. For erasing a selected block, the common source line (hereinafter, CSL) corresponding to the selected block is connected to a high voltage level, and the CSLs corresponding to the unselected blocks are also connected with the high voltage level. In this context, the term GCSL denotes a global common source line or a global common source line signal, and the term CSL denotes a common source line or a common source line signal.
FIG. 1 schematically illustrates a NAND flash memory with a GCSL architecture. A memory array 11 of the NAND flash memory includes Q blocks BLK(q), where q=1˜Q. Each block BLK(q) includes M transistor strings MS(q,1)˜MS(q,M). For example, the transistor string MS(1,1) denotes the first transistor string in the first block BLK(1), the transistor string MS(1,M) denotes the M-th transistor string in the first block BLK(1), the transistor string MS(Q,1) denotes the first transistor string in the Q-th block BLK(Q), and the transistor string MS(Q,M) denotes the M-th transistor string in the Q-th block BLK(Q). The rest may be deduced by analogy.
The blocks BLK(1)˜BLK(Q) of the NAND flash memory are electrically connected with a global common source line GCSL through the corresponding common source lines CSL(1)˜CSL(Q), respectively. In FIG. 1, the block BLK(k) marked by oblique lines denotes a selected block to be erased. As shown in FIG. 1, the block BLK(1) is the selected block.
For erasing the block BLK(1), an erase voltage Vcsl with a high voltage level (for example, a 20V-program pulse) is provided to the global common source line GCSL. In other words, the erase voltage Vcsl in the high voltage level state is provided to all of the common source lines CSL(1)˜CSL(Q). Since the block BLK(1) is the selected block, the cells corresponding to the transistor strings MS(1,1)˜MS(1,M) are erased according to the erase voltage Vcsl from the common source line CSL(1). However, the transistor strings of the unselected block, for example, the transistor strings MS(Q,1)˜MS(Q,M) of the block BLK(Q), are possibly suffered from unexpected influenced by the erase voltage Vcsl from the common source line CSL(Q).
Since the block BLK(Q) is the unselected block, the erase voltage Vcsl may result in a gate-induced-drain-leakage (hereinafter, GIDL) phenomenon on the terminals of the transistor strings MS(Q,1)˜MS(Q,M). The GIDL phenomenon may adversely affect the programming results of the cells and further result in erase interference. In addition to the region between the gate terminal and the drain terminal, the GIDL phenomenon possibly occurs between the gate terminal and the source terminal. As the length of the channel region and the thickness of the oxide layer are continuously decreased, the influence of the GIDL phenomenon on the NAND flash memory becomes more obvious.